Project F

Welcome to Project F. A little oasis of FPGA design and tutorials.

Mandelbrot in Verilog

News: December 2022

Verilog Vectors and Arrays


Sine Scroller

News: September 2022

Castle Drawing

News: June 2022

Lib: clock/xd

Display Signals

Racing the Beam

News: November 2021

Multiplication with FPGA DSPs

News: October 2021

News: September 2021

Numbers in Verilog

News: August 2021

Animated Shapes

News: July 2021


News: June 2021

Verilog Simulation with Verilator and SDL

News: May 2021

FPGA Sine Lookup Table

Hello Arty - Part 3

Project F Verilog Library

2D Shapes

Hello Nexys - Part 2

Lines and Triangles

Verilog Lint with Verilator

Square Root in Verilog

iCE40 FPGA Toolchain on Linux

Hello Nexys - Part 1


Hardware Sprites

Life on Screen

FPGA Memory Types


Division in Verilog

Video Timings: VGA, SVGA, 720p, 1080p

Ad Astra

Fixed Point Numbers in Verilog

Beginning FPGA Graphics

Hello Arty - Part 2

Hello Arty - Part 1

Initialize Memory in Verilog

FPGA Tooling on Ubuntu 20.04