Division is a fundamental arithmetic operation; one we take for granted in most contexts. FPGAs are different; Verilog can’t synthesize division: we need to do it ourselves. In this FPGA recipe, we’re going to look at a simple division algorithm for positive integers and fixed-point numbers. This method takes one cycle per bit: 32 cycles for 32-bit numbers. Revised 2020-07-06. Feedback to @WillFlux is most welcome. Division Defined Before we get to the design, we need to be familiar with some terminology. Read more

To work with standard monitors and TVs, you need to use the correct video timings. This recipe includes the timings for four standard display modes using analogue VGA, DVI, HDMI, or DisplayPort: 640x480 (VGA), 800x600 (SVGA), 1280x720, and 1920x1080 all at 60 Hz. CRT monitors typically support higher refresh rates in addition to 60 Hz, such as 72 and 85 Hz, but most LCD monitors do not. There are an increasing number of televisions and monitors that do support high refresh rates, but these are beyond the scope of this guide. Read more

In this series, we’ll be exploring FPGA graphics of all kinds, from the simplest static square, through Pong and the Mandelbrot set, to bitmaps, text scrollers, and even 3D modelling. There’s no microcontroller in any of these designs: they’re simple logic described in SystemVerilog. New to the series? Start with Exploring FPGA Graphics. Before framebuffers were ubiquitous, it was necessary to generate your graphics a line, or even a pixel, at a time. Read more

Sometimes you need more precision than integers can provide, but floating-point computation is not trivial (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers fast; we can take advantage of that with a fixed-point approach. This post is part of a series of handy recipes to solve common FPGA development problems. Read more

In all beginnings dwells a magic force Herman Hesse, Stages from The Glass Bead Game Welcome to Exploring FPGA Graphics with Project F. In this series, we’ll be experimenting with FPGA graphics of all kinds, from a static square, through Pong and the Mandelbrot set, to bitmaps, text scrollers, and even 3D modelling. There’s no microcontroller in any of these designs: they’re simple logic described in SystemVerilog. This post is a quick introduction to generating graphics with FPGAs: you’ll learn about display signals and simple colour graphics. Read more

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. You might be surprised how far counting takes you: by the end of this tutorial, you’ll be creating RGB lighting effects worthy of a cheesy gaming PC. Read more

People who are really serious about software should make their own hardware. Alan Kay, Creative Think seminar, 1982 This three-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Arty A7 board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program in Arduino, Python, or JavaScript, then you shouldn’t have any trouble. Read more

It’s common for a simulation or firmware to need data loading into a memory array, ram, or rom. Fortunately, Verilog provides the $readmemh and $readmemb functions for this very purpose. Unfortunately, there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This article explains the syntax and provides plenty of examples, including how to do this in Xilinx Vivado. This post is part of a series of handy recipes to solve common FPGA development problems. Read more

In this post, I test common FPGA tools for compatibility with Ubuntu 20.04 (AKA Focal Fossa), and my regular desktop OS: Pop!_OS 20.04. These tests are in no way exhaustive: I have tried using the applications as I usually do to exercise the main functionality. For me, the biggest gain in moving to 20.04 has been the responsiveness of the desktop. Tested: IceStorm Tools, nextpnr, nMigen, Verilator, Vivado, Yosys In Progress: Quartus Last updated 2020-06-05 follow WillFlux for future updates. Read more