Project F

Welcome to Project F. A little oasis of FPGA design and tutorials.

News: April 2023

News: April 2023

Vivado Tcl Build Script

Vivado Tcl Build Script

Mandelbrot in Verilog

Mandelbrot in Verilog

News: December 2022

News: December 2022

Verilog Vectors and Arrays

Verilog Vectors and Arrays

Rasterbars

Rasterbars

Sine Scroller

Sine Scroller

News: September 2022

News: September 2022

Castle Drawing

Castle Drawing

News: June 2022

News: June 2022

Lib: clock/xd

Lib: clock/xd

Display Signals

Display Signals

Racing the Beam

Racing the Beam

News: November 2021

News: November 2021

Multiplication with FPGA DSPs

Multiplication with FPGA DSPs

News: October 2021

News: October 2021

News: September 2021

News: September 2021

Numbers in Verilog

Numbers in Verilog

News: August 2021

News: August 2021

Animated Shapes

Animated Shapes

News: July 2021

News: July 2021

SPRAM on iCE40 FPGA

SPRAM on iCE40 FPGA

News: June 2021

News: June 2021

Verilog Simulation with Verilator and SDL

Verilog Simulation with Verilator and SDL

News: May 2021

News: May 2021

FPGA Sine Lookup Table

FPGA Sine Lookup Table

Hello Arty - Part 3

Hello Arty - Part 3

Verilog Library Announcement

Verilog Library Announcement

2D Shapes

2D Shapes

Hello Nexys - Part 2

Hello Nexys - Part 2

Lines and Triangles

Lines and Triangles

Verilog Lint with Verilator

Verilog Lint with Verilator

Square Root in Verilog

Square Root in Verilog

iCE40 FPGA Toolchain on Linux

iCE40 FPGA Toolchain on Linux

Hello Nexys - Part 1

Hello Nexys - Part 1

Framebuffers

Framebuffers

Hardware Sprites

Hardware Sprites

Life on Screen

Life on Screen

FPGA Memory Types

FPGA Memory Types

FPGA Pong

FPGA Pong

Division in Verilog

Division in Verilog

Video Timings: VGA, SVGA, 720p, 1080p

Video Timings: VGA, SVGA, 720p, 1080p

Ad Astra

Ad Astra

Fixed Point Numbers in Verilog

Fixed Point Numbers in Verilog

Beginning FPGA Graphics

Beginning FPGA Graphics

Hello Arty - Part 2

Hello Arty - Part 2

Hello Arty - Part 1

Hello Arty - Part 1

Initialize Memory in Verilog

Initialize Memory in Verilog

FPGA Tooling on Ubuntu 20.04

FPGA Tooling on Ubuntu 20.04