27 April 2021

Project F Verilog Library

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA beginners and hackers. Over the last couple of years, I’ve built up a small collection of handy Verilog modules as part of this blog. The Library brings these modules together with documentation and test benches to make them more accessible. Just bear in mind that I’m an enthusiastic amateur; my designs are unlikely to pass muster with language lawyers.

I’m always happy to receive constructive feedback; if you spot a bug or have an idea to improve the Library, open an issue on GitHub or get in touch with @WillFlux.

Library Areas

  • Clock - clock generation (PLL) and domain crossing
  • Display - display timings, framebuffer, DVI/HDMI output
  • Essential - handy modules for many designs
  • Graphics - drawing lines and shapes
  • Maths - divide, LFSR, square root…
  • Memory - roms and ram designs, including BRAM

NB. Documentation is being added throughout May and June 2021.

Module Testing

Project F tests these designs in simulation and on real hardware.

  • Synthesized with Yosys and Vivado
  • Include test benches (currently for Vivado but Verilator will be added soon)
  • Tested on Arty (Xilinx 7 Series) and iCEBreaker (Lattice iCE40) boards
  • Linted with Verilator


We use a few choice features of SystemVerilog to make Verilog more pleasant:

  • always_comb and always_ff to make intent clear and catch mistakes
  • $clog2 to calculate widths
  • enum to make finite state machines easier to work with
  • logic type to save messing with wire and reg
  • Matching names in module instances: .clk_pix, instead of .clk_pix(clk_pix),

I believe these features are helpful, especially for beginners. However, if you need to use an older Verilog standard, you can adapt these designs without too much trouble.

PS. The library photo used in the social media card for this post comes from Stewart Butterfield and is licensed under a Creative Commons licence.

©2021 Will Green, Project F