11 June 2021

Verilog Simulation with Verilator and SDL

It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer. The thought of creating a graphical simulation can be intimidating, but it’s surprisingly simple: you can get a simulation running in under an hour. Read more

30 May 2021

News: May 2021

As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month. I thought it would be interesting to share a few of these in a monthly news post. What do you think? Let me know via @WillFlux or open an issue on GitHub. Blog In May, I added two blog posts: Hello Arty Part 3 and FPGA Sine Lookup Table. Hello Arty is my introductory series for the Digilent Arty board. Read more

27 May 2021

FPGA Sine Lookup Table

In this FPGA recipe, we’re going to look at a straightforward method for generating sine and cosine using a lookup table. There are more precise methods, but this one is fast and simple and will suffice for many applications. This post is part of a series of handy recipes to solve common FPGA development problems. There are also posts on fixed-point numbers, division, and square root. Draft post: fixes and improvements to come. Read more

17 May 2021

Hello Arty - Part 3

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In this third instalment, we build a countdown timer and model traffic lights. There’s a lot to get through this time: enums, case statements, button debouncing, shift registers, and the all-important finite state machine. If you’re new to the series, start with part 1. A version for the Nexys Video will be available soon. Draft post: fixes and improvements to come. Read more

27 April 2021

Project F Verilog Library

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA beginners and hackers. Over the last couple of years, I’ve built up a small collection of handy Verilog modules as part of this blog. The Library brings these modules together with documentation and test benches to make them more accessible. Read more

17 March 2021

2D Shapes

Welcome back to Exploring FPGA Graphics. This time we’re going to build on our work in lines and triangles by drawing more shapes and filling them in before using our framebuffer to animate them. In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how displays work, race the beam with Pong, animate starfields and sprites, paint Michelangelo’s David, simulate life with bitmaps, draw lines and shapes, and finally render simple 3D models. Read more

11 February 2021

Hello Nexys - Part 2

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Nexys Video. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. New to the series? Start with part 1. This post is also available for the Arty. Updated 2021-05-17. Get in touch with @WillFlux or open an issue on GitHub. Read more

28 January 2021

Lines and Triangles

Welcome back to Exploring FPGA Graphics. It’s time to turn our attention to drawing. Most modern computer graphics come down to drawing triangles and colouring them in. So, it seems fitting to begin our tour of drawing with triangles and the straight lines that form them. This post will implement Bresenham’s line algorithm in Verilog, creating lines, triangles, and even a cube (our first sort-of-3D graphic). In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. Read more

31 December 2020

Verilog Lint with Verilator

Hardware design can be unforgiving, so it pays to use any advantage you can get. Verilator is a Verilog simulator and C++ compiler that also supports linting: statically analysing your designs for issues. Not only can Verilator spot problems your synthesis tool might overlook, but it also runs quickly. Updated 2021-04-01. Feedback to @WillFlux is most welcome. Installing Verilator Verilator is available in most Linux distribution repos and will run on Windows Subsystem for Linux. Read more

22 December 2020

Square Root in Verilog

The square root is useful in many circumstances, including statistics, graphics, and signal processing. In this FPGA recipe, we’re going to look at a straightforward digit-by-digit square root algorithm for integer and fixed-point numbers. There are lower-latency methods, but this one is simple, using only subtraction and bit shifts. This post is part of a series of handy recipes to solve common FPGA development problems. There are also posts on fixed-point numbers, division, and sine & cosine. Read more

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