Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in. This month, iCE40 SPRAM takes centre stage, filled triangles add graphical goodness, we learn that Linux will fit on an iCEBreaker, and discover FPGAs on Mars. If you have any comments, share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read older news. SPRAM on iCE40 FPGA There was one new blog post this month: SPRAM on iCE40 FPGA. Read more

The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as SPRAM. SPRAM blocks are much larger than BRAM but are limited to a single port and 16-bit data bus. In this quick FPGA recipe, we learn how to use SPRAM with Yosys and contrast it with Block RAM. If you want to learn more about other FPGA memory, see FPGA Memory Types. Read more

Project F news is your monthly update on the project, with tasty tips and links thrown in. Last month’s issue was well received, so I’m continuing with the experiment. June wasn’t the easiest of months, with a stint of COVID self-isolation1, but I’m happy to have written about Verilator and SDL. If you have any comments, find me on Twitter @WillFlux, or open an issue on GitHub. See the latest news or read July 2021. Read more

It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer. The thought of creating a graphical simulation can be intimidating, but it’s surprisingly simple: you can get a simulation running in under an hour. Read more

As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month. I thought it would be interesting to share a few of these in a monthly news post. What do you think? Let me know via @WillFlux or open an issue on GitHub. See the latest news or read June 2021. Blog In May, I added two blog posts: Hello Arty Part 3 and FPGA Sine Lookup Table. Read more

In this FPGA recipe, we’re going to look at a straightforward method for generating sine and cosine using a lookup table. There are more precise methods, but this one is fast and simple and will suffice for many applications. This post is part of a series of handy recipes to solve common FPGA development problems. There are also posts on fixed-point numbers, division, and square root. Updated 2021-06-28. Get in touch with @WillFlux or open an issue on GitHub. Read more

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In this third instalment, we build a countdown timer and model traffic lights. There’s a lot to get through this time: enums, case statements, button debouncing, shift registers, and the all-important finite state machine. A version for the Nexys Video will be available soon. New to the series? Start with part 1. Draft post: fixes and improvements to come. Read more

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA beginners and hackers. Over the last couple of years, I’ve built up a small collection of handy Verilog modules as part of this blog. The Library brings these modules together with documentation and test benches to make them more accessible. Read more

Welcome back to Exploring FPGA Graphics. This time we’re going to build on our work in lines and triangles with rectangles, circles, and filled shapes. We’ll finish off this part by drawing a castle using our shapes. In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how displays work, race the beam with Pong, animate starfields and sprites, paint Michelangelo’s David, simulate life with bitmaps, draw lines and shapes, and finally render simple 3D models. Read more

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Nexys Video. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. This post is also available for the Arty. New to the series? Start with part 1. Updated 2021-06-28. Get in touch with @WillFlux or open an issue on GitHub. Read more