This FPGA demo effect renders four animated rasterbars. I created this effect with benjamin.computer for All You Need, a Chapterhouse prod released at Revision 2022. For an introduction to rasterbars and other simple graphics effects, check out Racing the Beam. The design was originally for a custom Artix-7 dev board, but this version runs on the Digilent Arty or as a Verilator/SDL simulation on your computer. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) Read more

This FPGA demo effect renders a horizontally scrolling message along a sine wave. I created this effect with benjamin.computer for All You Need, a Chapterhouse prod released at Revision 2022. The design was originally for a custom Artix-7 dev board, but this version runs on the Digilent Arty or as a Verilator/SDL simulation on your computer. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) What is a Sine Scroller? Read more

Welcome to Project F news for July, August, and September 2022. There are four blog posts to cover and plans for the remainder of 2022. Watch out for more news in December 2022. For more frequent updates on new blog posts and FPGA designs, follow @WillFlux (Mastodon) or @WillFlux (Twitter). You can also find me on 1BitSquared Discord and open a GitHub Issue if you spot a bug or have a feature request. Read more

In this FPGA demo, we use multiple shapes (rectangles, triangles, circles) to render a simple picture of a castle. We don’t use any software or CPU, just shape rasterization and finite state machines. As our FPGA graphics capabilities improve, I’ll add more features to this drawing. Stay tuned. The design runs on the Digilent Arty or as a Verilator/SDL simulation on your computer. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) Read more

Project F news is back! It’s been a while, so this edition covers the first half of 2022. There are six new blog posts to cover as well as plans for the next few months. News will now be quarterly, with the next update in late September 2022. For more frequent updates on new blog posts and FPGA designs, follow @WillFlux (Mastodon) or @WillFlux (Twitter). You can also find me on 1BitSquared Discord and open a GitHub Issue if you spot a bug or have a feature request. Read more

Sometimes you need to send a single pulse from one clock domain to another. This is a simple case of clock domain crossing or CDC. This post uses the xd module from the Project F Library to handle such situations simply and safely. This post was last updated in October 2022. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) Sponsor My Work If you like what I do, consider sponsoring me on GitHub. Read more

Welcome back to Exploring FPGA Graphics. Last time, we played Pong against our FPGA; this time, we revisit displays signals and learn about palettes and indexed colour. This post was last updated in June 2022. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. Read more

Welcome back to Exploring FPGA Graphics. Last time, we got introduction to FPGA graphics; now, we’re ready to put our graphical skills to work with some simple demo effects. I hope these examples inspire you to create your own effects and improve your hardware design skills. This post was last updated in November 2022. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. Read more

Welcome to your November news from Project F. This month’s new blog post covers multiplication with DSPs, plus there are loads of interesting links and an FPGA advent calendar. I’m also happy to report that the main Project F repo projf-explore passed 200 stars on GitHub. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. The Project F blog is resting over the winter. Read more

Welcome back to my series covering mathematics and algorithms with FPGAs. Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by introductory guides: multiplication with DSPs. This post was last updated in November 2022. New to the series? Start with Numbers in Verilog. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) Series Outline Numbers in Verilog - introduction to numbers in Verilog Verilog Vectors and Arrays (coming soon) Fixed-Point Numbers in Verilog - precision without complexity Multiplication with FPGA DSPs (this post) - efficient multiplication with DSPs More maths in 2023 Sponsor My Work Read more

Welcome to October’s update from Project F. This month, we build a rainbow from circles, learn more about numbers in Verilog, find a UART in the library, and hear about exciting FPGA projects from Ben Blundell and Rob Shelton. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the November 2021 news or see the news archive. Filled Circles I’ve added a new filled circle drawing module to the Verilog Library. Read more

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. This month I began a new series on Maths & Algorithms, added a new rotation demo, and started a new blog on computing history. September also saw the release of Yosys 0.10 and the sad death of Sir Clive Sinclair. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read more

Welcome to my ongoing series covering mathematics and algorithms with FPGAs. This series begins with the basics of Verilog numbers, then considers fixed-point, division, square roots and CORDIC before covering more complex algorithms, such as data compression. In this first post, we consider integers, dig into the challenges of signed numbers and expressions, and then finish with a bit of arithmetic. This post was completely revised in November 2022. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) Read more

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. August saw my first circle drawn, new graphics designs for iCEBreaker, improved build instructions, and the first draft of a new post covering animated graphics and double buffering. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the September 2021 news or see the news archive. Read more

Welcome back to Exploring FPGA Graphics. In the final part of our introductory graphics series, we’re looking at animation. We’ve already seen animation with hardware sprites, but double buffering gives us maximum creative freedom with fast, tear-free motion. We’ll be making extensive use of our designs from 2D Shapes, so have a look back at that post if you need a refresher on drawing shapes. This post was revised in October 2022. Read more

Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in. This month, iCE40 SPRAM takes centre stage, filled triangles add graphical goodness, we learn that Linux will fit on an iCEBreaker, and discover FPGAs on Mars. If you have any comments, share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the August 2021 news or see the news archive. Read more

The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as SPRAM. SPRAM blocks are much larger than BRAM but are limited to a single port and 16-bit data bus. In this quick how to, we learn how to use SPRAM with Yosys and contrast it with Block RAM. If you want to learn more about other FPGA memory, see FPGA Memory Types. Read more

Project F news is your monthly update on the project, with tasty tips and links thrown in. Last month’s issue was well received, so I’m continuing with the experiment. June wasn’t the easiest of months, with a stint of COVID self-isolation1, but I’m happy to have written about Verilator and SDL. If you have any comments, find me on Twitter @WillFlux, or open an issue on GitHub. Read the July 2021 news or see the news archive. Read more

It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer. The thought of creating a graphical simulation can be intimidating, but it’s surprisingly simple: you’ll have your first simulation running in under an hour. Read more

As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month. I thought it would be interesting to share a few of these in a monthly news post. What do you think? Let me know via @WillFlux or open an issue on GitHub. Read the June 2021 news or see the news archive. Blog In May, I added two blog posts: Hello Arty Part 3 and FPGA Sine Lookup Table. Read more