Welcome back to my series covering mathematics and algorithms with FPGAs. I was initially going to look at real numbers in this part, but Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by introductory guides: multiplication with DSPs. We’ll cover real numbers in the next post. New to the series? Start with Numbers in Verilog. This post is a draft: improvements and additional content to come. Read more

Welcome to October’s update from Project F. This month, we build a rainbow from circles, learn more about numbers in Verilog, find a UART in the library, and hear about exciting FPGA projects from Ben Blundell and Rob Shelton. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. This is the latest news post, but you can always browse the news archive. Filled Circles I’ve added a new filled circle drawing module to the Verilog Library. Read more

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. This month I began a new series on Maths & Algorithms, added a new rotation demo, and started a new blog on computing history. September also saw the release of Yosys 0.10 and the sad death of Sir Clive Sinclair. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read more

Welcome to my new series covering mathematics and algorithms with FPGAs. Whatever hardware you’re designing, you’re likely to be working with numbers. This series begins with the basics of Verilog numbers, covers simple mathematics, including division and CORDIC, before looking at more complex algorithms, such as data compression. In this first post, we examine how integers (whole numbers) are represented and dig into the challenges of signed numbers in Verilog. Read more

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. August saw my first circle drawn, new graphics designs for iCEBreaker, improved build instructions, and the first draft of a new post covering animated graphics and double buffering. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the September 2021 news or see the news archive. Read more

Welcome back to Exploring FPGA Graphics. In the final part of our introductory graphics series, we’re looking at animation. We’ve already seen animation with hardware sprites, but double buffering gives us maximum creative freedom with fast, tear-free motion. We’ll be making extensive use of our designs from 2D Shapes, so have a look back at that post if you need a refresher on drawing shapes. In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. Read more

Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in. This month, iCE40 SPRAM takes centre stage, filled triangles add graphical goodness, we learn that Linux will fit on an iCEBreaker, and discover FPGAs on Mars. If you have any comments, share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the August 2021 news or see the news archive. Read more

The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as SPRAM. SPRAM blocks are much larger than BRAM but are limited to a single port and 16-bit data bus. In this quick FPGA recipe, we learn how to use SPRAM with Yosys and contrast it with Block RAM. If you want to learn more about other FPGA memory, see FPGA Memory Types. Read more

Project F news is your monthly update on the project, with tasty tips and links thrown in. Last month’s issue was well received, so I’m continuing with the experiment. June wasn’t the easiest of months, with a stint of COVID self-isolation1, but I’m happy to have written about Verilator and SDL. If you have any comments, find me on Twitter @WillFlux, or open an issue on GitHub. Read the July 2021 news or see the news archive. Read more

It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer. The thought of creating a graphical simulation can be intimidating, but it’s surprisingly simple: you’ll have your first simulation running in under an hour. Read more