24 June 2022

News: June 2022

Project F news is back! It’s been a while, so this edition covers the first half of 2022. There are six new blog posts to cover as well as plans for the next few months. News will now be quarterly, with the next update in late September 2022. For more frequent updates on new blog posts and FPGA designs, follow @WillFlux (Mastodon) or @WillFlux (Twitter). You can also find me on 1BitSquared Discord and open a GitHub Issue if you spot a bug or have a feature request. Read more

15 June 2022

Lib: clock/xd

Sometimes you need to send a single pulse from one clock domain to another. This is a simple case of clock domain crossing or CDC. This post uses the xd module from the Project F Library to handle such situations simply and safely. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) NB. Additional content will be added to this post over summer 2022. Sponsor My Work If you like what I do, consider sponsoring me on GitHub. Read more

7 May 2022

Display Signals

Welcome back to Exploring FPGA Graphics. Last time, we played Pong against our FPGA; this time, we revisit displays signals and learn about palettes and indexed colour. This post was last updated in June 2022. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. Read more

12 March 2022

Racing the Beam

Welcome back to Exploring FPGA Graphics. Last time, we got introduction to FPGA graphics; now, we’re ready to put our graphical skills to work with some simple demos. I hope these examples inspire you to create your own demos and improve your hardware design skills. This post was last updated in June 2022. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. Read more

3 December 2021

News: November 2021

Welcome to your November news from Project F. This month’s new blog post covers multiplication with DSPs, plus there are loads of interesting links and an FPGA advent calendar. I’m also happy to report that the main Project F repo projf-explore passed 200 stars on GitHub. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. The Project F blog is resting over the winter. Read more

27 November 2021

Multiplication with FPGA DSPs

Welcome back to my series covering mathematics and algorithms with FPGAs. I was initially going to look at real numbers in this part, but Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by introductory guides: multiplication with DSPs. We’ll cover real numbers in the next post. This post was last updated in December 2021. New to the series? Read more

31 October 2021

News: October 2021

Welcome to October’s update from Project F. This month, we build a rainbow from circles, learn more about numbers in Verilog, find a UART in the library, and hear about exciting FPGA projects from Ben Blundell and Rob Shelton. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the November 2021 news or see the news archive. Filled Circles I’ve added a new filled circle drawing module to the Verilog Library. Read more

9 October 2021

News: September 2021

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. This month I began a new series on Maths & Algorithms, added a new rotation demo, and started a new blog on computing history. September also saw the release of Yosys 0.10 and the sad death of Sir Clive Sinclair. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read more

30 September 2021

Numbers in Verilog

Welcome to my new series covering mathematics and algorithms with FPGAs. Whatever hardware you’re designing, you’re likely to be working with numbers. This series begins with the basics of Verilog numbers, covers simple mathematics, including division and CORDIC, before looking at more complex algorithms, such as data compression. This post was last updated in February 2022. In this first post, we examine how integers (whole numbers) are represented and dig into the challenges of signed numbers in Verilog. Read more

3 September 2021

News: August 2021

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. August saw my first circle drawn, new graphics designs for iCEBreaker, improved build instructions, and the first draft of a new post covering animated graphics and double buffering. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the September 2021 news or see the news archive. Read more

31 August 2021

Animated Shapes

Welcome back to Exploring FPGA Graphics. In the final part of our introductory graphics series, we’re looking at animation. We’ve already seen animation with hardware sprites, but double buffering gives us maximum creative freedom with fast, tear-free motion. We’ll be making extensive use of our designs from 2D Shapes, so have a look back at that post if you need a refresher on drawing shapes. This post was last updated in February 2022. Read more

4 August 2021

News: July 2021

Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in. This month, iCE40 SPRAM takes centre stage, filled triangles add graphical goodness, we learn that Linux will fit on an iCEBreaker, and discover FPGAs on Mars. If you have any comments, share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the August 2021 news or see the news archive. Read more

30 July 2021

SPRAM on iCE40 FPGA

The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as SPRAM. SPRAM blocks are much larger than BRAM but are limited to a single port and 16-bit data bus. In this quick how to, we learn how to use SPRAM with Yosys and contrast it with Block RAM. If you want to learn more about other FPGA memory, see FPGA Memory Types. Read more

1 July 2021

News: June 2021

Project F news is your monthly update on the project, with tasty tips and links thrown in. Last month’s issue was well received, so I’m continuing with the experiment. June wasn’t the easiest of months, with a stint of COVID self-isolation1, but I’m happy to have written about Verilator and SDL. If you have any comments, find me on Twitter @WillFlux, or open an issue on GitHub. Read the July 2021 news or see the news archive. Read more

11 June 2021

Verilog Simulation with Verilator and SDL

It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer. The thought of creating a graphical simulation can be intimidating, but it’s surprisingly simple: you’ll have your first simulation running in under an hour. Read more

30 May 2021

News: May 2021

As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month. I thought it would be interesting to share a few of these in a monthly news post. What do you think? Let me know via @WillFlux or open an issue on GitHub. Read the June 2021 news or see the news archive. Blog In May, I added two blog posts: Hello Arty Part 3 and FPGA Sine Lookup Table. Read more

27 May 2021

FPGA Sine Lookup Table

In this how to, we’re going to look at a straightforward method for generating sine and cosine using a lookup table. There are more precise methods, but this one is fast and simple and will suffice for many applications. This post was last updated in October 2021. There are also posts on fixed-point numbers, division, and square root. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) Sponsor My Work Read more

17 May 2021

Hello Arty - Part 3

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In this third instalment, we build a countdown timer and model traffic lights. There’s a lot to get through this time: enums, case statements, button debouncing, shift registers, and the all-important finite state machine. This post was last updated in December 2021. New to the series? Start with part 1. Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter) Read more

27 April 2021

Project F Verilog Library

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA hackers and beginners. Over the last couple of years, I’ve built up a small collection of handy Verilog modules. The Library brings these modules together with documentation and test benches to make them more accessible. Read more

17 March 2021

2D Shapes

Welcome back to Exploring FPGA Graphics. Building on our designs in lines and triangles, we’ll draw rectangles, filled triangles and circles. We’ll finish off this part by drawing a castle with our shapes. This post was last updated in January 2022. New version with updated framebuffer design coming summer 2022. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. Read more

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