## 1 July 2020

# Division in Verilog

Division is a fundamental arithmetic operation; one we take for granted in most contexts. FPGAs are different; Verilog can’t synthesize division: we need to do it ourselves. In this FPGA recipe, we’re going to look at a simple division algorithm for positive integers and fixed-point numbers. This method takes one cycle per bit: 32 cycles for 32-bit numbers.
Revised 2020-07-28. Feedback to @WillFlux is most welcome.
Division Defined Before we get to the design, it helps be familiar with some terminology.
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