# Tag: Maths

## RISC-V Assembler: Multiply Divide

RISC-V Assembler: Multiply DivideInteger multiply and divide instructions form the optional **M** extension. Making multiplication and division optional keeps the base instruction set simple and reduces the size of the smallest RISC-V core. This post includes a brief overview of common RISC-V extensions. Read More...

## RISC-V Assembler: Shift

RISC-V Assembler: ShiftThis RISC-V assembler post covers shift instructions, such as **sll**, **srl**, and **srai**. I also explain how to use shift instructions to quickly multiply and divide by powers of two. Read More...

## RISC-V Assembler: Logical

RISC-V Assembler: LogicalThis RISC-V assembler post covers bitwise logical instructions, such as **and**, **not**, and **xori**. Bitwise instructions carry out the specified operator on each bit of the sources in turn. Read More...

## RISC-V Assembler: Arithmetic

RISC-V Assembler: ArithmeticThis series will help you learn and understand 32-bit RISC-V instructions and programming. The first part looks at load immediate, addition, and subtraction. We’ll also cover sign extension and pseudoinstructions. Read More...

## Mandelbrot in Verilog

Mandelbrot in VerilogThis FPGA demo uses fixed-point multiplication and a small framebuffer to render the Mandelbrot set. You can navigate around the complex plane using buttons on your dev board. Read More...

## Verilog Vectors and Arrays

Verilog Vectors and ArraysWelcome back to my series covering mathematics and algorithms with FPGAs. In this part, we dig into vectors and arrays, including slicing, configurable widths, for loops, and bit and byte ordering. Read More...

## Multiplication with FPGA DSPs

Multiplication with FPGA DSPsWelcome back to my series covering mathematics and algorithms with FPGAs. Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by FPGA authors: multiplication with DSPs. Read More...

## Numbers in Verilog

Numbers in VerilogWelcome to my ongoing series covering mathematics and algorithms with FPGAs. This series begins with the basics of Verilog numbers, then considers fixed-point, division, square roots and CORDIC before covering more complex algorithms, such as data compression. Read More...

## FPGA Sine Lookup Table

FPGA Sine Lookup TableIn this how to, we’re going to look at a straightforward method for generating sine and cosine using a lookup table. There are more precise methods, but this one is fast and simple and will suffice for many applications. Read More...

## Square Root in Verilog

Square Root in VerilogThe square root is useful in many circumstances, including statistics, graphics, and signal processing. In this how to, we’re going to look at a straightforward digit-by-digit square root algorithm for integer and fixed-point numbers. There are lower-latency methods, but this one is simple, using only subtraction and bit shifts. Read More...

## Life on Screen

Life on ScreenIn this FPGA demo we’ll experiment with Game of Life, a cellular automaton created by prolific mathematician John Conway in 1970. Read More...

## Division in Verilog

Division in VerilogDivision is a fundamental arithmetic operation we take for granted. FPGAs include dedicated hardware to perform addition, subtraction, and multiplication and will infer the necessary logic. Division is different: we need to do it ourselves. This post looks at a straightforward division algorithm for positive integers before extending it to cover fixed-point numbers and signed numbers. Read More...

## Fixed Point Numbers in Verilog

Fixed Point Numbers in VerilogSometimes you need more precision than integers can provide, but floating-point computation is not trivial (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers fast; we can take advantage of that with a fixed-point approach. Read More...