Welcome to October’s update from Project F. This month, we build a rainbow from circles, learn more about numbers in Verilog, find a UART in the library, and hear about exciting FPGA projects from Ben Blundell and Rob Shelton. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. This is the latest news post, but you can always browse the news archive. Filled Circles I’ve added a new filled circle drawing module to the Verilog Library. Read more

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. This month I began a new series on Maths & Algorithms, added a new rotation demo, and started a new blog on computing history. September also saw the release of Yosys 0.10 and the sad death of Sir Clive Sinclair. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read more

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. August saw my first circle drawn, new graphics designs for iCEBreaker, improved build instructions, and the first draft of a new post covering animated graphics and double buffering. Want to get in touch? Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the September 2021 news or see the news archive. Read more

Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in. This month, iCE40 SPRAM takes centre stage, filled triangles add graphical goodness, we learn that Linux will fit on an iCEBreaker, and discover FPGAs on Mars. If you have any comments, share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read the August 2021 news or see the news archive. Read more

Project F news is your monthly update on the project, with tasty tips and links thrown in. Last month’s issue was well received, so I’m continuing with the experiment. June wasn’t the easiest of months, with a stint of COVID self-isolation1, but I’m happy to have written about Verilator and SDL. If you have any comments, find me on Twitter @WillFlux, or open an issue on GitHub. Read the July 2021 news or see the news archive. Read more

As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month. I thought it would be interesting to share a few of these in a monthly news post. What do you think? Let me know via @WillFlux or open an issue on GitHub. Read the June 2021 news or see the news archive. Blog In May, I added two blog posts: Hello Arty Part 3 and FPGA Sine Lookup Table. Read more

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA hackers and beginners. Over the last couple of years, I’ve built up a small collection of handy Verilog modules. The Library brings these modules together with documentation and test benches to make them more accessible. Read more