Verilog Library

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA hackers and beginners. Over the last few years, I’ve built up a small collection of handy Verilog modules. The Library brings these modules together with documentation and test benches to make them more accessible.

Design Source

You can find all the library designs in the Project F git repo:

  • Clock - clock generation (PLL) and domain crossing
  • Display - display timings, framebuffer, DVI/HDMI output
  • Essential - handy modules for many designs
  • Graphics - drawing lines and shapes
  • Maths - divide, LFSR, square root, sine…
  • Memory - ROM and RAM designs, including BRAM and SPRAM
  • UART - UART (serial) transmitter/receiver

Blog Posts

The following modules have dedicated blog posts:

  • clock/xd - simple clock domain crossing
  • maths/lfsr - linear-feedback shift register (coming soon)

Additional library posts in 2023.

Get in touch with @WillFlux or join me on GitHub Discussions and 1BitSquared Discord.

©2023 Will Green, Project F