Tag: Vivado

Vivado Tcl Build Script

20 Apr 2023 Vivado Tcl Build Script

Are you tired of firing up the Vivado GUI to build an FPGA project? You can automate your Xilinx FPGA build using a little Tcl. And you don’t even need to know any Tcl. Building your design from a script also comes in handy for continuous integration (CI) and Makefiles. Plus, I’ll show you how to quickly program your dev board with openFPGALoader. Read More...

Hello Nexys - Part 1

04 Nov 2020 Hello Nexys - Part 1

This two-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Nexys Video board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program with Python or JavaScript, you shouldn’t have any trouble. Read More...

Hello Arty - Part 1

24 Apr 2020 Hello Arty - Part 1

This three-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Arty A7 board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program with Python or JavaScript, you shouldn’t have any trouble. Read More...

Initialize Memory in Verilog

16 Apr 2020 Initialize Memory in Verilog

It’s common for a simulation or firmware to need data loading into a memory array, ram, or rom. Fortunately, Verilog provides the $readmemh and $readmemb functions for this very purpose. Unfortunately, there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This how to explains the syntax and provides plenty of examples, including how to do this in Yosys and Xilinx Vivado. Read More...