1 January 2020

Project F Site Map

New to Project F? Check out About Project F and Recommended FPGA Sites.

Verilog Library

The Project F Library includes handy Verilog designs from across Project F.
Read the Verilog Library Announcement or visit the Library on GitHub:

  • Clock - clock generation (PLL) and domain crossing
  • Display - display timings, framebuffer, DVI/HDMI output
  • Essential - handy modules for many designs
  • Graphics - drawing lines and shapes
  • Maths - divide, LFSR, square root, sine…
  • Memory - ROM and RAM designs, including BRAM and SPRAM
  • UART - UART (serial) transmitter/receiver

FPGA Graphics

Learn graphics at the hardware level, create games and demos, improve your FPGA design skills:

Maths and Algorithms with FPGAs

Stay tuned for more parts in 2022.

Hello

An introduction to FPGA development and Verilog with the Digilent Arty or Nexys Video boards:

Cookbook

Hardware & Devices

Maths

Tools & Testing

News

Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter)

©2022 Will Green, Project F