17 May 2021

Hello Arty - Part 3

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In this third instalment, we build a countdown timer and model traffic lights. There’s a lot to get through this time: enums, case statements, button debouncing, shift registers, and the all-important finite state machine. A version for the Nexys Video will be available soon. New to the series? Start with part 1. Draft post: fixes and improvements to come. Read more

27 April 2021

Project F Verilog Library

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA hackers and beginners. Over the last couple of years, I’ve built up a small collection of handy Verilog modules. The Library brings these modules together with documentation and test benches to make them more accessible. Read more

17 March 2021

2D Shapes

Welcome back to Exploring FPGA Graphics. Building on our designs in lines and triangles, we’ll draw rectangles, filled triangles and circles. We’ll finish off this part by drawing a castle with our shapes. In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how displays work, race the beam with Pong, animate starfields and sprites, paint Michelangelo’s David, simulate life with bitmaps, draw lines and shapes, and create smooth animation with double buffering. Read more

11 February 2021

Hello Nexys - Part 2

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Nexys Video. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. This post is also available for the Arty. New to the series? Start with part 1. Updated 2021-06-28. Get in touch with @WillFlux or open an issue on GitHub. Read more

28 January 2021

Lines and Triangles

Welcome back to Exploring FPGA Graphics. It’s time to turn our attention to drawing. Most modern computer graphics come down to drawing triangles and colouring them in. So, it seems fitting to begin our tour of drawing with triangles and the straight lines that form them. This post will implement Bresenham’s line algorithm in Verilog, creating lines, triangles, and even a cube (our first sort-of-3D graphic). In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. Read more

31 December 2020

Verilog Lint with Verilator

Hardware design can be unforgiving, so it pays to use any advantage you can get. Verilator is a Verilog simulator and C++ compiler that also supports linting: statically analysing your designs for issues. Not only can Verilator spot problems your synthesis tool might overlook, but it also runs quickly. Verilator is also great for graphics simulation with SDL. Updated 2021-07-20. Share your thoughts with @WillFlux or find me on 1BitSquared Discord. Read more

22 December 2020

Square Root in Verilog

The square root is useful in many circumstances, including statistics, graphics, and signal processing. In this FPGA recipe, we’re going to look at a straightforward digit-by-digit square root algorithm for integer and fixed-point numbers. There are lower-latency methods, but this one is simple, using only subtraction and bit shifts. This post is part of a series of handy recipes to solve common FPGA development problems. There are also posts on fixed-point numbers, division, and sine & cosine. Read more

11 November 2020

Building iCE40 FPGA Toolchain on Linux

Since I tested FPGA development tools on Ubuntu 20.04, there have been requests for more posts on FPGA tooling. In this post, I provide a quick guide to building an open-source FPGA toolchain for iCE40 boards, such as iCEBreaker. I plan to cover ECP5 FPGAs in a future version. This guide is designed for Ubuntu or Pop!_OS 20.04, but should be straightforward to adjust to your own distro. These instructions will work on Windows Subsystem for Linux (WSL), but there’s no USB support in WSL, so you can’t program boards under WSL. Read more

4 November 2020

Hello Nexys - Part 1

This three-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Nexys Video board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program with Python or JavaScript, you shouldn’t have any trouble. I find working with FPGAs gives me a sense of delight so often lacking in modern software development. There’s something profoundly satisfying about designing at the hardware level, be it drawing graphics on a screen, producing sound from a speaker, or even implementing your own CPU from scratch. Read more

30 October 2020


Welcome back to Exploring FPGA Graphics. In the previous two parts, we worked with sprites, but another approach is needed as graphics become more complex. Instead of drawing directly to the screen, we draw to a framebuffer, which is read out to the screen. This post provides an introduction to framebuffers and how to scale them up. We’ll also learn how to fizzlefade graphics Wolfenstein 3D style. In the next part, we’ll use a framebuffer to visualize a simulation of life. Read more

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