Sometimes you need more precision than integers can provide, but floating-point computation is not trivial (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers fast; we can take advantage of that with a fixed-point approach. This post is part of a series of handy recipes to solve common FPGA development problems. Read more

Welcome to Exploring FPGA Graphics. In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. We start by learning how displays work, before racing the beam with Pong, starfields and sprites, simulating life with bitmaps, drawing lines and triangles, and finally creating simple 3D models. I’ll be writing and revising this series throughout 2020. In this first post, we learn how computer displays work and animate simple shapes with an FPGA. Read more

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. You might be surprised how far counting takes you: by the end of this tutorial, you’ll be creating RGB lighting effects worthy of a cheesy gaming PC. Read more

This three-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Arty A7 board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program in Arduino, Python, or JavaScript, then you shouldn’t have any trouble. This series is also available for the Nexys Video. I find working with FPGAs gives me a sense of delight so often lacking in modern software development. Read more

It’s common for a simulation or firmware to need data loading into a memory array, ram, or rom. Fortunately, Verilog provides the $readmemh and $readmemb functions for this very purpose. Unfortunately, there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This article explains the syntax and provides plenty of examples, including how to do this in Xilinx Vivado. If you want to learn more about FPGA memory itself, see FPGA Memory Types. Read more

In this post, I test common FPGA tools for compatibility with Ubuntu 20.04 (AKA Focal Fossa), and my regular desktop OS: Pop!_OS 20.04. These tests are in no way exhaustive: I have tried using the applications as I usually do to exercise the main functionality. I have also included instructions for building the tools from source when available. This is my final planned update for this post (July 2020). Tested: IceStorm Tools, nextpnr, nMigen, Verilator, Vivado, Yosys Incomplete: Quartus Updated 2020-07-30. Read more