Project F

ECP5 FPGA Clock Generation

Thu, 30 Jan 2025 00:00:00 +0000

Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outlines the architecture of ECP5 PLL and provides several practical examples to get you started with generating custom clock frequencies. Generating your own clock frequencies is much more straightforward than it first appears.

RISC-V Assembler: Compiler Explorer

Tue, 15 Oct 2024 00:00:00 +0000

The Godbolt Compiler Explorer is a fantastic tool for assembler programmers. In this post, I show you how to use Compiler Explorer to generate RISC-V assembly code and offer some ideas to make best use of this tool.

RISC-V Assembler Cheat Sheet

Fri, 14 Jun 2024 00:00:00 +0000

This cheat sheet provides a handy guide to 32-bit RISC-V instructions. I’ve aimed it at software developers, so group instructions by purpose and include common pseudoinstructions.

RISC-V Assembler: Multiply Divide

Fri, 17 May 2024 00:00:00 +0000

Integer multiply and divide instructions form the optional M extension. Making multiplication and division optional keeps the base instruction set simple and reduces the size of the smallest RISC-V core. This post includes a brief overview of common RISC-V extensions.

RISC-V Assembler: Jump and Function

Tue, 30 Apr 2024 00:00:00 +0000

This RISC-V assembler post begins by examining the RISC-V jump instructions: jal and jalr. Jump instructions are the basis of functions, so we’ll then dig into function calls, the RISC-V ABI, calling convention, and how to use the stack.

RISC-V Assembler: Branch Set

Tue, 19 Mar 2024 00:00:00 +0000

This RISC-V assembler post covers branch and set instructions, such as beq, bltu, bgez, and slt. We’ll also cover the zero register, program counter, condition codes, and multi-word addition.

RISC-V Assembler: Load Store

Thu, 15 Feb 2024 00:00:00 +0000

This RISC-V assembler post covers load and store instructions, such as lw, sw, and lbu. We also cover memory alignment, addressing modes, and loading symbol addresses.

RISC-V Assembler: Shift

Tue, 30 Jan 2024 00:00:00 +0000

This RISC-V assembler post covers shift instructions, such as sll, srl, and srai. I also explain how to use shift instructions to quickly multiply and divide by powers of two.

RISC-V Assembler: Logical

Mon, 29 Jan 2024 00:00:00 +0000

This RISC-V assembler post covers bitwise logical instructions, such as and, not, and xori. Bitwise instructions carry out the specified operator on each bit of the sources in turn.

RISC-V Assembler: Arithmetic

Mon, 15 Jan 2024 00:00:00 +0000

This series will help you learn and understand 32-bit RISC-V instructions and programming. The first part looks at load immediate, addition, and subtraction. We’ll also cover sign extension and pseudoinstructions.

News: April 2023

Sat, 29 Apr 2023 00:00:00 +0000

Welcome to the latest Project F news covering the first part of 2023. In this edition, we sail the sea of chaos, round out division, automate Vivado with Tcl, and uncover openFPGALoader and cocotb.

Vivado Tcl Build Script

Thu, 20 Apr 2023 00:00:00 +0000

Are you tired of firing up the Vivado GUI to build an FPGA project? You can automate your Xilinx FPGA build using a little Tcl. And you don’t even need to know any Tcl. Building your design from a script also comes in handy for continuous integration (CI) and Makefiles. Plus, I’ll show you how to quickly program your dev board with openFPGALoader.

Mandelbrot in Verilog

Tue, 07 Mar 2023 00:00:00 +0000

This FPGA demo uses fixed-point multiplication and a small framebuffer to render the Mandelbrot set. You can navigate around the complex plane using buttons on your dev board.

News: December 2022

Wed, 04 Jan 2023 00:00:00 +0000

Happy New Year and welcome to the latest Project F news covering the end of 2022. This update is packed with maths, graphics and the usual smattering of bits and pieces.

Verilog Vectors and Arrays

Tue, 13 Dec 2022 00:00:00 +0000

Welcome back to my series covering mathematics and algorithms with FPGAs. In this part, we dig into vectors and arrays, including slicing, configurable widths, for loops, and bit and byte ordering.

Rasterbars

Wed, 23 Nov 2022 00:00:00 +0000

This FPGA demo effect renders four animated rasterbars. I created this effect with benjamin.computer for All You Need, a Chapterhouse prod released at Revision 2022.

Sine Scroller

Mon, 24 Oct 2022 00:00:00 +0000

This FPGA demo effect renders a horizontally scrolling message along a sine wave. I created this effect with benjamin.computer for All You Need, a Chapterhouse prod released at Revision 2022.

News: September 2022

Thu, 22 Sep 2022 00:00:00 +0000

Welcome to Project F news for July, August, and September 2022. There are four blog posts to cover and plans for the remainder of 2022.

Castle Drawing

Sun, 11 Sep 2022 00:00:00 +0000

In this FPGA demo, we use multiple shapes (rectangles, triangles, circles) to render a simple picture of a castle. We don’t use any software or CPU, just shape rasterization and finite state machines. This Verilog design runs on the Digilent Arty A7 or as a Verilator/SDL simulation on your computer.

News: June 2022

Fri, 24 Jun 2022 00:00:00 +0000

Project F news is back! It’s been a while, so this edition covers the first half of 2022. There are six new blog posts to cover as well as plans for the next few months.

Lib: clock/xd

Wed, 15 Jun 2022 00:00:00 +0000

Sometimes you need to send a single pulse from one clock domain to another. This is a simple case of clock domain crossing or CDC. This post uses the xd module from the Project F Library to handle such situations simply and safely.

Display Signals

Sat, 07 May 2022 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. Last time, we played Pong against our FPGA; this time, we revisit displays signals and learn about palettes and indexed colour.

Racing the Beam

Sat, 12 Mar 2022 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. Last time, we got an introduction to FPGA graphics; let’s put our new graphical skills to work with some simple demo effects. I hope these examples inspire you to create your own effects and improve your hardware design skills.

News: November 2021

Fri, 03 Dec 2021 00:00:00 +0000

Welcome to your November news from Project F. This month’s new blog post covers multiplication with DSPs, plus there are loads of interesting links and an FPGA advent calendar. I’m also happy to report that the main Project F repo projf-explore passed 200 stars on GitHub.

Multiplication with FPGA DSPs

Sat, 27 Nov 2021 00:00:00 +0000

Welcome back to my series covering mathematics and algorithms with FPGAs. Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by FPGA authors: multiplication with DSPs.

News: October 2021

Sun, 31 Oct 2021 00:00:00 +0000

Welcome to October’s update from Project F. This month, we build a rainbow from circles, learn more about numbers in Verilog, find a UART in the library, and hear about exciting FPGA projects from Ben Blundell and Rob Shelton.

News: September 2021

Sat, 09 Oct 2021 00:00:00 +0000

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. This month I began a new series on Maths & Algorithms, added a new rotation demo, and started a new blog on computing history. September also saw the release of Yosys 0.10 and the sad death of Sir Clive Sinclair.

Numbers in Verilog

Thu, 30 Sep 2021 00:00:00 +0000

Welcome to my ongoing series covering mathematics and algorithms with FPGAs. This series begins with the basics of Verilog numbers, then considers fixed-point, division, square roots and CORDIC before covering more complex algorithms, such as data compression.

News: August 2021

Fri, 03 Sep 2021 00:00:00 +0000

Project F news is your monthly bowl of FPGA goodness with tasty tips and links from other developers mixed in. August saw my first circle drawn, new graphics designs for iCEBreaker, improved build instructions, and the first draft of a new post covering animated graphics and double buffering.

Animated Shapes

Tue, 31 Aug 2021 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. In the final part of our introductory graphics series, we’re looking at animation. We’ve already seen animation with hardware sprites, but double buffering gives us maximum creative freedom with fast, tear-free motion.

News: July 2021

Wed, 04 Aug 2021 00:00:00 +0000

Project F news is your monthly update on the FPGA project, with tasty tips and links from other developers thrown in. This month, iCE40 SPRAM takes centre stage, filled triangles add graphical goodness, we learn that Linux will fit on an iCEBreaker, and discover FPGAs on Mars.

SPRAM on iCE40 FPGA

Fri, 30 Jul 2021 00:00:00 +0000

The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as SPRAM. SPRAM blocks are much larger than BRAM but are limited to a single port and 16-bit data bus.

News: June 2021

Thu, 01 Jul 2021 00:00:00 +0000

Project F news is your monthly update on the project, with tasty tips and links thrown in. Last month’s issue was well received, so I’m continuing with the experiment. June wasn’t the easiest of months, with a stint of COVID self-isolation, but I’m happy to have written about Verilator and SDL.

Verilog Simulation with Verilator and SDL

Fri, 11 Jun 2021 00:00:00 +0000

It can be challenging to test your FPGA or ASIC graphics designs. You can perform low-level behavioural simulations and examine waveforms, but you also need to verify how the video output will appear on the screen. By combining Verilator and SDL, you can build Verilog simulations that let you see your design on your computer.

News: May 2021

Sun, 30 May 2021 00:00:00 +0000

As well as the occasional big blog post, I make many smaller FPGA discoveries and Project F updates each month. I thought it would be interesting to share a few of these in a monthly news post. What do you think?

FPGA Sine Lookup Table

Thu, 27 May 2021 00:00:00 +0000

In this how to, we’re going to look at a straightforward method for generating sine and cosine using a lookup table. There are more precise methods, but this one is fast and simple and will suffice for many applications.

Hello Arty - Part 3

Mon, 17 May 2021 00:00:00 +0000

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In this third instalment, we build a countdown timer and model traffic lights. There’s a lot to get through this time: enums, case statements, button debouncing, shift registers, and the all-important finite state machine.

Verilog Library Announcement

Tue, 27 Apr 2021 00:00:00 +0000

2D Shapes

Wed, 17 Mar 2021 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. In 2D Shapes, we build on what we learned from Lines and Triangles in two ways: drawing new shapes and learning to colour them in. We’ll start with rectangles and filled triangles before moving on to circles. These basic shapes make it possible to create a wide variety of graphics and user interfaces.

Hello Nexys - Part 2

Thu, 11 Feb 2021 00:00:00 +0000

Welcome back to our two-part FPGA tutorial with SystemVerilog and the Digilent Nexys Video. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation.

Lines and Triangles

Thu, 28 Jan 2021 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. It’s time to turn our attention to drawing. Most modern computer graphics come down to drawing triangles and colouring them in. So, it seems fitting to begin our drawing tour with triangles and the straight lines that form them. This post will implement Bresenham’s line algorithm in Verilog and create lines, triangles, and even a cube (our first sort-of 3D).

Verilog Lint with Verilator

Thu, 31 Dec 2020 00:00:00 +0000

Hardware design can be unforgiving, so it pays to use any advantage you can get. Verilator is a Verilog simulator and C++ compiler that also supports linting: statically analysing your designs for issues. Not only can Verilator spot problems your synthesis tool might overlook, but it also runs quickly.

Square Root in Verilog

Tue, 22 Dec 2020 00:00:00 +0000

The square root is useful in many circumstances, including statistics, graphics, and signal processing. In this how to, we’re going to look at a straightforward digit-by-digit square root algorithm for integer and fixed-point numbers. There are lower-latency methods, but this one is simple, using only subtraction and bit shifts.

iCE40 FPGA Toolchain on Linux

Wed, 11 Nov 2020 00:00:00 +0000

In this post, I provide a quick guide to building an open-source FPGA toolchain for iCE40 boards, such as iCEBreaker, on Linux. This guide is designed for Ubuntu or Pop!_OS 20.04, but should be straightforward to adjust to your own distro.

Hello Nexys - Part 1

Wed, 04 Nov 2020 00:00:00 +0000

This two-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Nexys Video board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program with Python or JavaScript, you shouldn’t have any trouble.

Framebuffers

Fri, 30 Oct 2020 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. In the previous part, we worked with sprites, but another approach is needed as graphics become more complex. Instead of drawing directly to the screen, we draw to a bitmap, which is read out to the screen. This post provides an introduction to framebuffers and how to scale them up. We’ll also learn how to fizzlefade graphics Wolfenstein 3D style.

Hardware Sprites

Wed, 28 Oct 2020 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. In the previous part, we updated our display signals and learnt about colour palettes. This part shows you how to create fast, colourful graphics with minimal logic. Hardware sprites maintain much of the simplicity of our Pong design while offering greater creative freedom.

Life on Screen

Tue, 22 Sep 2020 00:00:00 +0000

In this FPGA demo we’ll experiment with Game of Life, a cellular automaton created by prolific mathematician John Conway in 1970.

FPGA Memory Types

Mon, 24 Aug 2020 00:00:00 +0000

Designing with FPGAs involves many types of memory, some familiar from other devices, but some that are specific to FPGAs. This how to gives a quick overview of the different flavours, together with their strengths and weaknesses, and some sample designs. This guide includes external memory types, such as SRAM and HBM, that are used in CPUs and GPUs, so much of what is said here is generally applicable, but the focus is on FPGAs.

FPGA Pong

Thu, 30 Jul 2020 00:00:00 +0000

Welcome back to Exploring FPGA Graphics. Last time, we raced the beam; this time, we’ll recreate the arcade classic, Pong and play against our FPGA.

Division in Verilog

Wed, 01 Jul 2020 00:00:00 +0000

Division is a fundamental arithmetic operation we take for granted. FPGAs include dedicated hardware to perform addition, subtraction, and multiplication and will infer the necessary logic. Division is different: we need to do it ourselves. This post looks at a straightforward division algorithm for positive integers before extending it to cover fixed-point numbers and signed numbers.

Video Timings: VGA, 720p, 1080p

Fri, 26 Jun 2020 00:00:00 +0000

This guide includes the timings for many standard display modes using analogue VGA, DVI, HDMI, or DisplayPort: 640x480 (VGA), 800x600 (SVGA), 1024x768 (XGA), 1280x720, and 1920x1080 (30 Hz and 60 Hz).

Ad Astra

Wed, 10 Jun 2020 00:00:00 +0000

This collection of related demos combines some of my earliest FPGA designs from 2018: simple sprites and an animated starfield generated with a linear-feedback shift register.

Fixed Point Numbers in Verilog

Tue, 26 May 2020 00:00:00 +0000

Sometimes you need more precision than integers can provide, but floating-point computation is not trivial (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers fast; we can take advantage of that with a fixed-point approach.

Beginning FPGA Graphics

Wed, 20 May 2020 00:00:00 +0000

Welcome to Exploring FPGA Graphics. In this series, we learn about graphics at the hardware level and get a feel for the power of FPGAs. We’ll learn how screens work, play Pong, create starfields and sprites, paint Michelangelo’s David, draw lines and triangles, and animate characters and shapes. Along the way, you’ll experience a range of designs and techniques, from memory and finite state machines to crossing clock domains and translating C algorithms into Verilog.

Hello Arty - Part 2

Wed, 06 May 2020 00:00:00 +0000

Welcome back to our three-part FPGA tutorial with SystemVerilog and the Digilent Arty A7. In part two, we’re going to learn about clocks and counting. Along the way, we’ll cover maintaining state with flip-flops, timing things with clock dividers, creating our first Verilog module, and controlling LEDs with pulse width modulation. You might be surprised how far counting takes you: by the end of this tutorial, you’ll be creating RGB lighting effects worthy of a cheesy gaming PC.

Hello Arty - Part 1

Fri, 24 Apr 2020 00:00:00 +0000

This three-part tutorial provides a quick introduction to FPGA development with SystemVerilog and the Digilent Arty A7 board. No prior experience of FPGA development is required, but basic knowledge of programming concepts is assumed. If you can write a simple program with Python or JavaScript, you shouldn’t have any trouble.

Initialize Memory in Verilog

Thu, 16 Apr 2020 00:00:00 +0000

It’s common for a simulation or firmware to need data loading into a memory array, ram, or rom. Fortunately, Verilog provides the $readmemh and $readmemb functions for this very purpose. Unfortunately, there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This how to explains the syntax and provides plenty of examples, including how to do this in Yosys and Xilinx Vivado.

FPGA Tooling on Ubuntu 20.04

Mon, 06 Apr 2020 00:00:00 +0000

In this post, I test common FPGA tools for compatibility with Ubuntu 20.04 (AKA Focal Fossa), and my regular desktop OS: Pop!_OS 20.04. These tests are in no way exhaustive: I have tried using the applications as I usually do to exercise the main functionality. I have also included instructions for building the tools from source when available.

About Project F