Verilog Library

I like to learn by doing, by trying things out and experimenting. However, this is hard with FPGAs; there’s a significant lack of practical Verilog designs online. The Project F Library is the latest part of my attempt to make things a little better for FPGA hackers and beginners. Over the last couple of years, I’ve built up a small collection of handy Verilog modules. The Library brings these modules together with documentation and test benches to make them more accessible.

Blog Posts

The following modules have dedicated blog posts:

  • clock/xd - simple clock domain crossing

Additional posts coming later in 2022.

GitHub

You can find all the designs in the Project F repo:

  • Clock - clock generation (PLL) and domain crossing
  • Display - display timings, framebuffer, DVI/HDMI output
  • Essential - handy modules for many designs
  • Graphics - drawing lines and shapes
  • Maths - divide, LFSR, square root, sine…
  • Memory - ROM and RAM designs, including BRAM and SPRAM
  • UART - UART (serial) transmitter/receiver

Get in touch: GitHub Issues, 1BitSquared Discord, @WillFlux (Mastodon), @WillFlux (Twitter)

©2022 Will Green, Project F