Project F

Tag: Memory

RISC-V Assembler: Load Store

RISC-V Assembler: Load Store

Part four of RISC-V assembler looks at load and store instructions, such as lw, sw, and lbu. We’ll also cover memory alignment, addressing modes, and loading symbol addresses. Read More...

SPRAM on iCE40 FPGA

SPRAM on iCE40 FPGA

The iCE40 UltraPlus distinguishes itself from the rest of the iCE40 FPGA family by including a relatively generous 1 Mb (128 KiB) of single port synchronous SRAM known as SPRAM. SPRAM blocks are much larger than BRAM but are limited to a single port and 16-bit data bus. Read More...

FPGA Memory Types

FPGA Memory Types

Designing with FPGAs involves many types of memory, some familiar from other devices, but some that are specific to FPGAs. This how to gives a quick overview of the different flavours, together with their strengths and weaknesses, and some sample designs. This guide includes external memory types, such as SRAM and HBM, that are used in CPUs and GPUs, so much of what is said here is generally applicable, but the focus is on FPGAs. Read More...

Initialize Memory in Verilog

Initialize Memory in Verilog

It’s common for a simulation or firmware to need data loading into a memory array, ram, or rom. Fortunately, Verilog provides the $readmemh and $readmemb functions for this very purpose. Unfortunately, there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This how to explains the syntax and provides plenty of examples, including how to do this in Yosys and Xilinx Vivado. Read More...