# Multiplication with FPGA DSPs

Welcome back to my series covering mathematics and algorithms with FPGAs. I was initially going to look at real numbers in this part, but Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by introductory guides: multiplication with DSPs. We’ll cover real numbers in the next post. This post was last updated in December 2021. New to the series?

# Numbers in Verilog

Welcome to my new series covering mathematics and algorithms with FPGAs. Whatever hardware you’re designing, you’re likely to be working with numbers. This series begins with the basics of Verilog numbers, covers simple mathematics, including division and CORDIC, before looking at more complex algorithms, such as data compression. This post was last updated in February 2022. In this first post, we examine how integers (whole numbers) are represented and dig into the challenges of signed numbers in Verilog.

# FPGA Sine Lookup Table

In this FPGA recipe, we’re going to look at a straightforward method for generating sine and cosine using a lookup table. There are more precise methods, but this one is fast and simple and will suffice for many applications. This post was last updated in October 2021. This post is part of a series of handy recipes to solve common FPGA development problems. There are also posts on fixed-point numbers, division, and square root.

# Square Root in Verilog

The square root is useful in many circumstances, including statistics, graphics, and signal processing. In this FPGA recipe, we’re going to look at a straightforward digit-by-digit square root algorithm for integer and fixed-point numbers. There are lower-latency methods, but this one is simple, using only subtraction and bit shifts. This post was last updated in June 2021. This post is part of a series of handy recipes to solve common FPGA development problems.

# Division in Verilog

Division is a fundamental arithmetic operation; one we take for granted in most contexts. FPGAs are different; Verilog can’t synthesize division: we need to do it ourselves. In this FPGA recipe, we’re going to look at a straightforward division algorithm for positive integers and fixed-point numbers. For integers, this method takes one cycle per bit: 32 cycles for 32-bit numbers. This post was last updated June 2021. This post is part of a series of handy recipes to solve common FPGA development problems.

# Fixed Point Numbers in Verilog

Sometimes you need more precision than integers can provide, but floating-point computation is not trivial (try reading IEEE 754). You could use a library or IP block, but simple fixed point maths can often get the job done with little effort. Furthermore, most FPGAs have dedicated DSP blocks that make multiplication and addition of integers fast; we can take advantage of that with a fixed-point approach. This post was last updated in May 2021.